All publicationsAmir Noohi
Conference2026

SagePTE: Co-Locating Guest and Host PTEs to Accelerate Virtual Memory Translation

Amir Noohi, Mostafa Derispour, Rodrigo Caetano de Oliveira Rocha, Antonio Barbalace, Artemiy Margaritov

IEEE/ACM International Symposium on Microarchitecture (MICRO)

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Abstract

Modern virtualization relies on lengthy two-dimensional address translation, where guest virtual addresses first map to guest physical addresses before resolving to host physical memory, resulting in up to 24 additional memory accesses. We introduce Pocket Dimension Page Tables (PDPTs)—a novel approach that securely embeds host translations within guest page table entries, eliminating the need for hypervisor intervention on page table updates while allowing to shorten page walks. PDPTs require isolated changes to the ISA, OS, and hardware page walker, and no changes to the guest OS, ensuring seamless integration into existing software stacks.

BibTeX

@inproceedings{noohi2026sagepte,
  author    = {Amir Noohi and Mostafa Derispour and Rodrigo Caetano de Oliveira Rocha and Antonio Barbalace and Artemiy Margaritov},
  title     = {{SagePTE: Co-Locating Guest and Host PTEs to Accelerate Virtual Memory Translation}},
  booktitle = {IEEE/ACM International Symposium on Microarchitecture (MICRO)},
  year      = {2026},
}