SagePTE: Co-Locating Guest and Host PTEs to Accelerate Virtual Memory Translation

Hardware-assisted virtualization relies on two-dimensional (2D) nested address translation, trading the costly software traps of Shadow Page Tables for high access-time latency. This overhead is heavily concentrated at the leaf of the page walk: the final host page-table traversal required to resolve the data page. To eliminate this bottleneck, we introduce SagePTE, a hardware-software co-design that bridges the gap between nested and shadow paging by shadowing only the leaf PTEs, directly in-place within the guest page table. By expanding the guest page table layout on-demand in host memory, SagePTE co-locates guest and host mappings into a unified 128-bit extended entry. To maintain strict isolation while guaranteeing trap-free leaf synchronization, our design seamlessly repurposes existing silicon primitives, such as 128-bit compare-and-swap logic. Zero-delay hardware access mediation within the core's memory execution path safely masks guest reads and upgrades guest writes, triggering automatic hardware synchronization. This allows the page walker to fetch both translations simultaneously and bypass the final host walk entirely. SagePTE operates purely beneath the virtualization boundary, supporting unmodified guests without para-virtualization. We formally verify SagePTE's isolation guarantees using Alloy and evaluate it on ARM, demonstrating average end-to-end speedups over nested translation of 1.30× with 4 KB pages and 1.22× with Transparent Huge Pages (THP).