
Amir Noohi
PhD Candidate
Institute for Computing Systems Architecture, University of Edinburgh
About Me
I'm a PhD Candidate at the University of Edinburgh's Institute for Computing Systems Architecture. My research focuses on advancing system architectures for modern computing challenges, spanning operating systems, network dataplanes, and distributed systems optimization.
Research Interests
Education
PhD
The University of Edinburgh
Operating Systems, Systems for ML, Distributed Systems, Virtualization
Dr. Antonio Barbalace & Dr. Boris Grot
(TBD) Distributed Shared Memory and CXL-based Memory Architectures for AI Workloads — combining RMAI and NTSM research on scalable memory solutions for large-scale AI inference and training.
Master of Science
Isfahan University of Technology
Computer Science
Dr. Massoud Reza Hashemi
NSwitch: A high-speed, protocol-independent programmable software switch for SDN networks. By bypassing the OS kernel and introducing NDB (an in-RAM protocol database), NSwitch enables dynamic protocol management via simple API calls without recompilation. Controllers can add, edit, or delete protocols instantly. Achieves 60 Gbps throughput, ~20 million packets/second, and 26 microseconds latency with only 3% overhead.
Bachelor of Science
Isfahan University of Technology
Computer Engineering
Dr. Elham Mahmoud Zadeh
Jinaro: An integrated sports venue management platform connecting users, coaches, and gym owners. The system addresses the challenge of finding suitable sports classes, provides employment opportunities for certified coaches, and enables facility owners to advertise their events and classes using modern IT technologies.
Recent News
Jul 2026: Paper accepted at MICRO '26: SagePTE: Co-Locating Guest and Host PTEs to Accelerate Virtual Memory Translation.
Jun 2026: I presented at Q2 2026 Huawei Workshop in Cambridge.
May 2026: Promoted to CPU Researcher at Huawei Cambridge Research Center, working on CPU optimization for AI agentic workloads.
May 2026: I attended EuroSys '26 as a student volunteer and presented our paper at the co-located EuroMLSys '26.
Mar 2026: Paper accepted at EuroMLSys '26: Towards a Solution to the Management Scaling Paradox in Distributed LLM Inference.
Mar 2026: Paper accepted at Middleware '26: NTSM: OS-Level Memory Middleware for Scaling AI Without Boundaries.
Dec 2025: I presented SagePTE at Q4 2025 Huawei Workshop in Cambridge.
Dec 2025: Started advising Hasan Alhussain (MSc) at University of Edinburgh.
Nov 2025: Started advising Arsh Kumar (BSc) at University of Edinburgh.
Sep 2025: Serving as Lead TA for Programming for Data Science at Scale course.
Mar 2025: I presented RMAI at EuroMLSys'25 in Rotterdam, Netherlands.
Mar 2025: I will be serving on the Shadow PC and AEC for EuroSys'25.
Jan 2025: Serving as Lead TA for Operating Systems course at University of Edinburgh.
Dec 2024: I presented at Q4 2024 Huawei Workshop in Cambridge.
Oct 2024: NFV-based SDN framework paper published in IEEE Access.
Oct 2024: Joined Huawei Technologies R&D UK as CPU Architect (Contractor).
Aug 2024: Started advising Saba Ebrahimi (MSc visiting intern from Shahid Beheshti University).
Jul 2024: My internship at Huawei Cambridge Research Center has begun!
Sep 2023: Started advising Zhengyi Chen and Tom Blackburn (UG Projects) at University of Edinburgh.
Jul 2023: Started advising Mostafa Derispour (BSc) at Isfahan University of Technology.
Jan 2023: My PhD at the University of Edinburgh has begun!
Sep 2022: Teaching Database course as Lecturer at Sharif University of Technology.
Aug 2021: My MSc is finished and I graduated Ranked 1st!
Sep 2019: My MSc at Isfahan University of Technology has begun!
Jun 2019: My BSc is finished and I graduated Ranked 1st!
Jun 2019: Directly admitted to MSc program as an outstanding student.
Sep 2015: My BSc in Computer Engineering at Isfahan University of Technology has begun!
Sep 2015: Ranked in Top 1% of Iranian University Entrance Exam.
Aug 2011: Founded HIGHHOST, my first web hosting company!
Publications
8 papers in systems & networking
Submitted to ASPLOS
Coming soon • 2027
Under Revision
Amir Noohi
ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)
Submitted to ATC
Coming soon • 2026
Under Revision
Amir Noohi
USENIX Annual Technical Conference (ATC)
Submitted to SoCC
Coming soon • 2026
Under Revision
Amir Noohi
ACM Symposium on Cloud Computing (SoCC)
SagePTE: Co-Locating Guest and Host PTEs to Accelerate Virtual Memory Translation
Amir Noohi, Mostafa Derispour, Rodrigo Caetano de Oliveira Rocha, Antonio Barbalace, Artemiy Margaritov
IEEE/ACM International Symposium on Microarchitecture (MICRO)
Modern virtualization relies on lengthy two-dimensional address translation, where guest virtual addresses first map to guest physical addresses before resolving to host physical memory, resulting in up to 24 additional memory accesses. We introduce Pocket Dimension Page Tables (PDPTs)—a novel approach that securely embeds host translations within guest page table entries, eliminating the need for hypervisor intervention on page table updates while allowing to shorten page walks. PDPTs require isolated changes to the ISA, OS, and hardware page walker, and no changes to the guest OS, ensuring seamless integration into existing software stacks.
Disaggregated LLM inference separates prefill and decode across nodes, relying on cross-node KV cache reuse (prefix caching) to reduce time-to-first-token (TTFT). Yet existing systems manage this cache entirely in user space, atop the very kernel that already handles memory mapping, page tables, and RDMA registration. We identify a management scaling paradox: user-space overhead from coordination RPCs, per-chunk locking, redundant memory copies, and RDMA transfer fragmentation grows to 79% of achievable TTFT as the cache warms, nearly doubling latency when caching should help most. We formalize this paradox as a TTFT decomposition model and validate it on the state-of-the-art LMCache + Mooncake stack atop vLLM. We then present RMC (Remote Memory for Cache), an in-kernel framework that extends OS-provided shared memory (/dev/shm) to cluster-wide scope via content-addressed Virtual Memory Regions (VMRs), where any node computes the address of any cached chunk by hashing its token content, requiring no coordination. Across four workloads, RMC achieves 1.1–1.3× TTFT reduction over LMCache + Mooncake and up to 2.1× over full recompute.
The rapid scaling of large language models—from hundreds of billions to trillions of parameters—has rendered distributed memory management the critical bottleneck in modern AI systems. Existing frameworks manage cross-node memory entirely in user space, incurring serialization overhead that consumes up to 76.7% of data transfer latency, memory amplification reaching up to 6.7× from intermediate buffers, and escalating coordination costs that compound with cluster size. These overheads are fundamental: commodity operating systems lack abstractions for TB-scale tensors, cross-node sharing, and the sequential, layer-granular access patterns characteristic of transformer workloads. We present NTSM, a kernel-space middleware that recasts distributed memory management as a first-class OS primitive. Implemented as a Linux kernel module with a minimal kernel modification (one exported symbol on x86), NTSM exposes a symmetric virtual address space across cluster nodes where applications access remote data through ordinary memory operations. Page faults trigger zero-copy RDMA transfers with automatic coherence enforcement via a directory-based M/S/I protocol operating at 32KB–2MB Virtual Memory Region granularity—matching the natural access grain of transformer layers while amortizing fault overhead. By executing in kernel space, NTSM directly manipulates page tables, pins memory for DMA, and manages TLB state, eliminating the serialization, buffer copies, and user-kernel transitions inherent to user-space approaches. NTSM integrates transparently with existing frameworks: 152 lines modified for PyTorch FSDP, 89 lines for Ray Parameter Server. Evaluation on a 34-node RDMA cluster with models up to 175B parameters demonstrates up to 6.5× speedup in distributed training memory operations, 4.4× reduction in time-to-first-token for inference, and 47% reduction in parameter server iteration time—establishing kernel-level memory management as a viable foundation for next-generation distributed AI infrastructure.
As AI models grow exponentially in size, memory has emerged as a critical bottleneck for inference at scale. While hardware solutions like Compute Express Link (CXL) promises to solve the problem of memory capacity and sharing, they require capital investment, and are not widely available. This paper presents RMAI, an in-kernel remote shared memory framework tailored for AI inference workloads, offering a transparent, scalable, and cost-effective software alternative to hardware-based memory expansion and sharing solutions.
Network programmability has always been a topic of interest to researchers. After introducing the concept of SDN, control-plane programmability is achieved. However, data-plane programmability remains a challenge in the context of network programmability. We propose an autonomous SDN-based framework that achieves flexible parsing of arbitrary protocol header fields in real-time using software switches based on the NFV concept.
Professional Experience
9 positions across 3 sectors
CPU Researcher
ContractorActiveHuawei Technologies Research & Development (UK) Ltd — Cambridge Research Center
Cambridge, England, United Kingdom
May 2026 - Present
1 month
Researching CPU architecture optimizations for AI agentic workloads.
CPU Architect
InternHuawei Technologies Research & Development (UK) Ltd — Cambridge Research Center
Cambridge, England, United Kingdom
Oct 2024 - Apr 2026
1 year 7 months
Leveraged the 128-bit extended PTEs developed during my internship to accelerate virtualized address translation. Designed and implemented a novel approach that fuses guest PTEs with host PTEs by securely relocating host translation metadata into the extended PTE space, achieving shadow page table performance levels without compromising security isolation. This work resulted in SagePTE, accepted at MICRO 2026. Additionally, developed extensive codebase and specifications exploring other applications of the additional 64-bit metadata space, including memory protection extensions, cache hints, and memory tiering annotations.
CPU Architect
InternHuawei Technologies Research & Development (UK) Ltd — Cambridge Research Center
Edinburgh, Scotland, United Kingdom
Jul 2024 - Oct 2024
3 months
Extended Linux kernel page table entries (Level 3 entries) to 128-bit and modified QEMU to support this feature. QEMU modifications: fixed two-stage address translation issues, resolved address translation during page table walk, added configurable 128-bit PTE toggle. Linux kernel modifications: fixed early page table issues before transitioning to C code, resolved stack pointer overlapping with page table due to increased size during early boot, fixed early boot device mapping (map_fdt), resolved page table allocation/deallocation during boot, fixed kmem_cache indexing issues, addressed SLUB allocator randomization issues, added PTE setter/getter functions exported for kernel code, added syscalls to set/get PTEs from user space, implemented configurable 128-bit PTE support option. Developed test cases: kernel module tests for PTE modifications, user space performance tests, syscall tests for PTE set/get operations.
CEO & Founder
FounderVSABT
Tehran Province, Iran
Jan 2021 - Jan 2023
2 years 1 month
Founded and led a domain brokerage platform that aggregates multiple domain registrar APIs to always offer customers the best available prices. Developed an intelligent system that automatically monitors domain pricing across registrars and seamlessly migrates customer domains between providers to maintain minimum costs. Built the complete technical infrastructure including API integrations, automated domain transfer workflows, price comparison engine, and customer management system.
CEO & Founder
FounderHIGHHOST
Isfahan, Iran
Aug 2011 - Jan 2023
11 years 6 months
Founded and operated a comprehensive web hosting company offering dedicated servers, virtual private servers (VPS), shared hosting, cPanel hosting, reseller hosting, and domain registration services. Built and managed the entire infrastructure including server provisioning, network configuration, customer billing systems, and 24/7 technical support. Scaled the business to serve thousands of customers with high availability and reliable hosting solutions.
Research Assistant
EmployeeIsfahan University of Technology
Isfahan, Iran
Sep 2019 - Sep 2022
3 years 1 month
Designed and implemented a novel NFV-based framework for autonomous protocol deployment in SDN networks. Extended the NSwitch architecture to support dynamic network function virtualization, enabling real-time packet processing with programmable action pipelines. Developed a protocol-independent parsing engine that allows controllers to deploy, modify, and chain virtual network functions without switch recompilation. This research resulted in a publication in IEEE Access demonstrating flexible data-plane programmability through software-based NFV integration.
Technical Product Manager
ContractorIAI Core Center
Isfahan Province, Iran
Feb 2020 - Jul 2020
6 months
Led the development of a patient-nurse communication platform for Iran Zamin Clinic, consisting of Android and web applications. The system enables nurses to remotely guide patients through their treatment plans, provide medication reminders and instructions, answer health-related questions, and monitor patient progress. Managed a cross-functional team of developers and designers, defined product requirements, coordinated sprint planning, and ensured timely delivery of features.
Cloud Engineer
ContractorIUT ECE Department
Isfahan, Iran
Dec 2019 - Feb 2020
3 months
Infrastructure: Architected and deployed a production-grade private cloud serving 100+ physical servers across 5 data center racks. Virtualization: Built the hypervisor layer using VMware ESXi 7.0 with vCenter Server for centralized management, vSphere HA for high availability, and DRS for dynamic resource scheduling. Orchestration: Integrated OpenNebula as the cloud management platform, enabling multi-tenant self-service provisioning, VM lifecycle management, and resource quota enforcement. Networking: Configured enterprise-grade network infrastructure including VLANs, distributed virtual switches, and link aggregation for redundancy. Storage: Implemented shared storage using NFS and iSCSI over dedicated storage networks with multipath I/O for failover. Monitoring: Deployed Prometheus and Grafana for infrastructure observability and alerting. Operations: Established automated backup policies, disaster recovery procedures, and comprehensive operational documentation.
Software Developer
InternIUT ECE Department
Isfahan, Iran
Apr 2018 - Jul 2019
1 year 4 months
Developed the backend for Jinaro project using Laravel (PHP), implementing RESTful APIs and database architecture. Managed DevOps responsibilities including CI/CD pipelines, server configuration, and deployment automation. Handled infrastructure provisioning, monitoring, and maintained production environments.
Teaching Experience
26 courses across 3 universities
Lead Teaching Assistant
Teaching Assistant
Lecturer
Teaching Assistant
Lead Teaching Assistant
Teaching Assistant
Students Advised
Mentoring the next generation of researchers
Alumni
9 studentsHonors & Awards
Recognition for research and academic excellence
Ph.D. Scholarship Award
School of Informatics, University of Edinburgh
Fully-funded 4-year PhD scholarship covering tuition fees and living expenses
Ranked 1st in M.Sc.
Isfahan University of Technology
Ranked 1st among all computer engineering students in Master's program
Ranked 1st in B.Sc.
Isfahan University of Technology
Ranked 1st among all computer engineering students in Bachelor's program
Direct Admission to M.Sc.
Isfahan University of Technology
Directly admitted to M.Sc. as an outstanding B.Sc. student
National Exceptional Talents Scholarship
Iran's National Foundation for Exceptional Talents
Monthly stipend award for exceptional academic performance
Top 1% in University Entrance Exam
Iranian National Exam
Top 1% in Iranian university entrance exam for B.Sc. and M.Sc.
Physics Olympiad - Ranked 7th
National Physics Olympiad
Ranked 7th in Physics Olympiad
Math Olympiad - Ranked 5th
National Math Olympiad
Ranked 5th in Math Olympiad
Talks & Presentations
Conference presentations and invited talks
Q2 2026 Huawei Workshop
Huawei Technologies Research & Development
RMC: Remote Memory for Cache
EuroMLSys 2026 Workshop
Q4 2025 Huawei Workshop
Huawei Technologies Research & Development
RMAI: Rethinking Memory for AI Inference
EuroMLSys 2025 Workshop
Q4 2024 Huawei Workshop
Huawei Technologies Research & Development
Academic Service
Contributions to the research community
EuroSys 2026
Supported on-site conference operations and assisted attendees
EuroSys 2025
Evaluated reproducibility and quality of research artifacts
EuroSys 2025
Evaluated reproducibility and quality of research artifacts
EuroSys 2025
Reviewed paper submissions as part of the shadow PC program
Technical Skills52 technologies
Get in Touch
Open to research collaborations, PhD advice, and industry projects
Room 1.19, School of Informatics
10 Crichton St, Edinburgh EH8 9AB
Institute for Computing Systems Architecture
University of Edinburgh, Edinburgh, UK